Akıllı sistemler ve uygulamaları dergisi

This study constructs an Adaptive Bayesian Experimental Design (ABED) model to enhance real-time probabilistic testing of semiconductors by inference and adaptive resource allocation. The model prioritizes the test-planning stage of a programmable logic device (PLD) as a sequence of decisions that maximizes expected information gain while operating under a cost and power budget. This framework reallocates Automatic Test Equipment (ATE) cycles to the more uncertain regions of a wafer by dynamically updating the ATE posterior distributions of the defect probability with conjugate prior distributions, purposefully crafted information-theoretic utility functions, and intelligent utility functions. Simulations with 10,000 devices across 20 ATE channels show an average test time reduction of 23.6%, an increase of 17.8% in precision of yield estimation, and a 35% reduction of posterior entropy gain over static test plans. The static 3D information gain manifolds with Bayesian convergence slopes show the system’s data efficiency and asymptotic stability and confirm its scalability to next generation semiconductor testing environments. The tests demonstrate the model as a robust baseline framework towards fully information driven self optimizing testing frameworks applicable to microelectronics, MEMS, and photonic circuits.